(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of performing p-type implantation in the Lightly Doped Diffusion (PLDD) area of a gate electrode, preventing diffusion of boron as the p-type impurity. This more specifically for gate electrodes with submicron channel length.
(2) Description of the Prior Art
Semiconductor technology has for many years made progress by a continued effort to decrease device dimensions in order to improve Integrated Circuit (IC) device performance. Metal Oxide Semiconductor Field Effect Transistor (MOSFET) devices form an increasing percentage of the total number of devices that are used in Integrated Circuit (IC) applications. MOSFET devices are expected to continue to increase in importance, it is expected that by the year 2000 MOSFET devices will constitute roughly 90% of the overall market. Reduction in device dimensions results in a reduction in device power consumption. It is an accepted rule in semiconductor technology that device speed varies inversely with the length of device features, device power consumption increases approximately with the square of the device feature length. Current semiconductor technology approaches feature size in the micron and sub-micron or 0.5 xcexcm range where a number of applications already use feature size of about 0.2 xcexcm.
Field Effect Transistors (FET) are used extensively in Ultra Large Scale Integration (ULSI) applications. FET devices are formed using gate electrodes, usually made of polysilicon, and adjacent self-aligned source/drain regions to which source/drain contact surfaces are established. In its basic form, a Metal Oxide Semiconductor (MOS) transistor has a gate electrode to which a voltage is applied. The gate is created on the surface of a silicon substrate, the voltage that is applied to the gate creates an electric field that is perpendicular to the interface between the gate electrode and the substrate. The areas in the substrate immediately adjacent to the gate electrode are doped, thereby varying their electric conductivity. These areas become the source and drain regions. By varying the voltage that is applied to the gate electrode, the electric field in the interface between the gate and the substrate can be varied and, with that, the current that flows between the source and the drain regions. This electric field controls the flow of current through the device from which the name of Field Effect Transistor has been derived.
The type of device that is created and the type of areas that are created in conjunction with the device are to a large extent determined by the type of dopant that is used and the processing conditions under which the dopants are applied. The creation of semiconductor devices typically starts with a bare monocrystalline silicon substrate, which is any material that can retain dopant ions. Isolated active regions are created in the surface of the substrate. The silicon substrate further receives p-type or n-type ions (impurity implants) for the creation of various conductivity regions in or on the surface of the substrate. The device features that are created in or on the surface of the substrate dictate the type of doping and the doping conditions. For instance, boron or phosphorous can be used as respectively p-type and n-type dopants and can be doped into polysilicon layers or into polycide gate electrodes.
MOS devices are typically created on the surface of a substrate after either a p-type or a n-type impurity has been implanted in the surface of the substrate, creating wells in this surface of either p-type or n-type conductivity. NMOS devices (also referred to as n-channel devices) are, after that, created on the surface of a p-type well, PMOS devices (also referred to as p-channel devices) are created on the surface of an n-type well. The type of channel underlying a MOS gate electrode is determined by the type of conductivity of the channel that is developed under the transverse electric field of the gate electrode. Therefore, in an n-channel of NMOS devices, the conductivity of the channel underlying the transverse electrical field of the gate electrode is of the conductivity type that is associated with n-type impurities such as arsenic or phosphorous. For p-channel (PMOS) devices, these impurities comprise boron or indium. After the gate electrode has been created, Lightly Doped Diffusions (LDD) are typically implanted in the surface of the substrate, self aligned with the gate electrode, whereby n-type impurities are use for the LDD regions of NMOS devices and p-type impurities for the LDD regions of PMOS devices. After this, the gate electrode is isolated by the formation of gate spacers on the sidewalls of the gate electrode, this is followed by forming the source and drain regions of the gate electrodes. For the source/drain implants the same type impurities are used as have been used for the LDD implants, the difference between the LDD implants and the source/drain implants is that the source/drain implants are typically performed at higher implant energy and dosage that the LDD implants. In this manner the p-type implants (for PMOS devices) of the source/drain regions (PS/D) and the n-type implants (for NMOS devices) of the source/drain regions (NS/D) penetrate deeper into the surface of the substrate than the corresponding p-type (PLDD) and n-type (NLDD) implants for the LDD regions.
Dual gate transistor design is the design where both NMOS and PMOS devices are created on the same chip. Earlier designs of Metal Oxide Semiconductor (MOS) devices primarily used PMOS design because only with p-channel devices using n+-doped polysilicon gates and uniform lightly doped n-substrates could acceptable values for Vt be attained. In its early history, the Complementary Metal Oxide Semiconductor (CMOS) transistor was considered to be only an extension of the design for MOS IC""s. Later advancements in fabrication technology, mostly due to improvements in ion implant techniques, allowed for PMOS devices to be replaced with NMOS devices. The larger drive current of NMOS devices results in faster speed of these devices, which results in NMOS devices becoming the dominant type of device in the IC industry. NMOS devices however exhibited severe limitations in power density and power dissipation, causing CMOS devices to become the dominant technology for IC device manufacturing. With the arrival of CMOS devices, a renewed interest in PMOS devices developed. CMOS employs both NMOS and PMOS devices to form logic elements. The advantage of CMOS is that its logic devices draw significant current only during the transition from one logic state to the other while drawing very little current between this transition.
The scaling of the CMOS devices in the sub-micrometer device range presents a major challenge. For the fabrication of pchannel and n-channel devices, n doped polysilicon gates are used resulting in functional asymmetry. A number of techniques have been used to assure that the p-channel and n-channel devices are completely symmetrical in their performance characteristics such as threshold voltages, device dimensions and doping while the p-channel device is, for ease of manufacturing, a surface channel device. These devices are made using undoped polysilicon for the gate structures that are simultaneously doped at the time that the source/drain regions of each type of device are implanted. This leads to special manufacturing problems caused by, among others, diffusion of impurity implants through the gate oxide into the channel region thereby changing the threshold voltage of the device. Another concern in creating dual-gate CMOS devices is that various dopants may inter-diffuse between adjacent regions, an effect that can become critical at high anneal and other processing temperatures.
Increased CMOS device speed however requires short channel length, the design of p-channel devices with short channel length presents unique problems mostly centered on methods of doping and pocket implants for the device and on the impact that these methods have on PMOS device characteristics. A technique used for instance to create deeper and narrower implants is to increase implant energy and implant dosage. This approach however may negate the self-alignment aspect of the implants where the gate electrode serves as a shield and the implants become in this way aligned around the gate electrode. The high implant energy and dosage may result in implant penetration through the gate electrode, thereby affecting the gate threshold voltage performance while the high implant energy and dosage may further affect the thin layer of gate oxide underlying the gate electrode. It is therefore critical to design an implant method and sequence where gate penetration by implant dopants is not a factor.
Various types of implants are used in the industry to create semiconductor devices. Implants can be a well implant, which is performed to provide a more uniform background doping in the surface of the substrate. A punch-through implant provides a channel with greater robustness to punch-through voltage. A thresh-hold implant sets the thresh-hold voltage of a device (like an IGFET).
A p-well implant can be provided by boron at a dose in the range of 1xc3x971012 to 1xc3x971013 atoms/cm2 and an energy in the range of 100 to 170 kilo-electron volts, a punch-through implant can be provided by boron at an dose in the range of 1xc3x971012 to 1xc3x971013 atoms/cm2 and an energy in the range of 40 to 100 kilo electron volts, the thresh-hold implant can be provided by boron at a dose in the range 1xc3x971012 to 1xc3x971013 atoms/cm2 and an energy in the range of 1 to 30 kilo electron volts. A channel implant can have a boron concentration on the order of 1xc3x971017 atoms/cm2. Implants can also use arsenic; this can form an n-doped region. A heavy doped implant for instance is 3-5xc3x971015/cm2 of arsenic at 50-80 keV.
Decreasing device dimensions has resulted in decreasing the channel length of gate electrodes, that is the lateral distance between the source and drain regions of the gate electrode is reduced to where this dimension approaches 0.2 xcexcm or less. As the channel length is reduced, the gate electrode must also be reduced in the vertical direction, which further brings with it a reduction in the distance that the source/drain regions can penetrate into the surface of the substrate. This latter requires precise control of the distribution of the impurity dopant of the source and drain regions. This problem is further aggravated where salicided regions are created on the surface of the source/drain regions in order to reduce contact resistivity to these regions. The selective growth of the salicide that is needed for good contact resistance with the metalization layer requires a reaction between the deposited layer of salicide material, for instance titanium, and the underlying silicon. The titanium that is formed on the surface of the contact regions (source/drain regions) must be wide enough to accommodate the photolithographic limitations in forming contact openings to the source/drain regions. This results in a wider device. Also, since silicon is consumed in this process, the junction depth of the source/drain regions is difficult to control and dopant depletion can occur in these regions. Furthermore, formation of the deep, heavily doped junctions for the source/drain regions can result in dopant diffusion under the gate region thereby reducing the effective channel length of the MOSFET, leading to the so-called xe2x80x9cshort channel effectxe2x80x9d.
One of the key factors that affects the reliability of FET devices of small geometry is caused by the shrinkage of the channel length and channel width. To overcome problems associate with short and narrow channel effects is therefore an important concern in the design of FET devices. Gate oxide integrity can also be negatively affected by the hot-carrier effect. If the carriers can acquire sufficient energy from the lateral electric field (the field parallel to the plane of the substrate surface), these carriers may transfer across the substrate to the gate oxide interface thereby affecting the oxide conduction band and, ultimately, its function of forming a gate oxide layer of electrical separation. The electric field barrier for electron injection is smaller than it is for hole injection. This problem is therefore more prominent in n-channel MOSFET""s because electrons form the charge carrier in the device channel.
Specifically addressed by the invention are concerns of gate electrode design that arise as the physical geometry of the gate electrode is reduced. With this reduction the channel length is also reduced, creating the previously indicated short channel effect. In particular, in creating PLDD structures for which boron is used as an impurity implant, the tendency of high diffusivity of boron into the surrounding silicon substrate affects the threshold voltage and the device drive current, thus affecting the PMOS device performance characteristics.
In a typical processing flow, PLDD implantation is performed before S/D implantation and anneal of the implanted impurities. This anneal step will further enhance the diffusion of the boron from the PLDD regions into the silicon underneath the gate electrode. This invention addresses this latter aspect of CMOS gate design.
U.S. Pat. No. 6,103,563 (Lukanc et al.) shows a process where the NLDD, NS/D and PS/D are formed and annealed, then PLDD is formed. See FIGS. 2a to 2h, also see col. 5, lines 7 to 43. In comparing U.S. Pat. No. 6,103,563 (Lukanc et al.) with the instant invention, it must be pointed out that U.S. Pat. No. 6,103,563 (Lukanc et al.) is not compatible with the salicide process. In addition, U.S. Pat. No. 6,103,563 (Lukanc et al.) is aimed at reducing the mask count and not at reducing the lateral diffusion of dopant. Even though the PS/D implant is performed prior to the PLDD implant, the photoresist mask is still in place at the time of the PS/D implant, which is not suitable for the S/D annealing process. Therefore, under U.S. Pat. No. 6,103,563 (Lukanc et al.) the S/D anneal must be performed after the PLDD implant and after the removal of the photoresist. This approach does not reduce lateral dopant diffusion.
U.S. Pat. No. 5,998,272 (Ishida et al.) discloses a xe2x80x9creverse LDDxe2x80x9d process where the LDD is formed after the S/D anneal. In comparing this invention with the instant invention, it must be pointed out that the process flow that is provided by U.S. Pat. No. 5,998,272 (Ishida et al.) is not compatible with the creation of borderless contacts. With zero exclusion, the borderless contact can, under U.S. Pat. No. 5,998,272 (Ishida et al.), land partially on the surface of the STI region. This may cause the occurrence of leakage current (between the contact to the source/drain regions and the surface of the STI regions) or, in a worst case scenario, a short may occur (between the contact to the S/D regions and the surface of the STI regions). In addition, the process flow of U.S. Pat. No. 5,998,272 (Ishida et al.) is not compatible with self-aligned contacts (SAC). The process that is provided by U.S. Pat. No. 5,998,272 (Ishida et al.) contains spacers or, even in the case where no spacers are provided, this approach is not suitable for the SAC process. Typically, the SAC process uses a hard mask for the gate electrode and uses nitride as an etch stop layer for the etching of the gate spacers.
U.S. Pat. No. 6,074,906 (Cheek et al.) and U.S. Pat. No. 5,399,506 (Tsukamoto) show related processes.
A principle objective of the invention is to reduce lateral diffusion of boron impurities into adjacent channel regions for application where a boron impurity is used as a p-type impurity implant for the creation of Lightly Doped Diffusion (LDD) regions for a PMOS device.
Another objective of the invention is to provide a method for the creation of CMOS devices whereby the diffusion of p-type LDD impurities that is caused by the anneal process of the LDD implant is removed.
Yet another objective of the invention is to provide a method for the elimination of PLDD diffusion of boron into adjacent silicon of the substrate that can be applied to the creation of PMOS devices that have a sub-micron channel length.
In accordance with the objectives of the invention a new method is provided for the creation of PLDD regions that is aimed at reducing lateral p-type impurity diffusion. The process starts with a silicon substrate on the surface of which gate electrodes have been created. An NLDD implantation is performed self-aligned with the NMOS gate electrode, a layer of oxide (oxide liner) is deposited over the structure over which a layer of nitride is deposited over which a first layer of top oxide is deposited. First gate spacers are formed by etching the first layer of top oxide, stopping on the nitride layer. NS/D and PS/D implants are performed self-aligned with respectively the NMOS and the PMOS devices, the S/D implantations are annealed. The first gate oxide spacers are removed, a PLDD implantation is performed self-aligned with the PMOS gate electrode. A second layer of top oxide is deposited over the structure and etched to form the second gate spacers on the sidewalls of the NMOS and PMOS gate electrodes. After this sequence of processing steps has been completed, the gate electrodes can be completed following conventional methods of gate electrode processing.